Ensuring reliable and high quality microelectronics products has remained the primary objective of semiconductor test for years. Successive technology nodes, design characteristics, design processes and other factors have caused an evolution of test schemes. New types of defects and patterns inevitably pose the questions of how sustainable current test schemes are and what matching design-for-test (DFT) methods may soon be needed. For example, it is unclear whether test data compression—the industry-proven mainstream DFT methodology of the last decade—will be capable of coping with the rapid rate of technological changes and the resultant test challenges. Interestingly, logic built-in self-test (LBIST), originally developed for board, system, and infield test, is now often used with test compression. This hybrid approach allows LBIST to rival the best manufacturing test techniques by providing the abilities to run at-speed power-aware tests and to reduce the test cost while preserving or augmenting LBIST and scan compression advantages.
Classical LBIST applications include detecting infant mortality defects during burn-in test or enabling the use of low-cost and/or low-speed testers that only provide power and clock signals. With a mass market driving automotive, mobile or healthcare systems, however, attempts to overcome the bottleneck of test data bandwidth have made the concept of combining logic BIST and test data compression a vital research and development area. The standard ISO 26262 defining functional safety features for automotive equipment applicable throughout the lifecycle of all electronic and electrical safety-related systems clearly calls for at least 90% single point fault coverage attainable in a very short period of test application time. Furthermore, as radio frequency transceivers are smaller than ever and consume less power, the semiconductor test industry is also embracing the opportunity to incorporate wireless communications into on-chip on-line LBIST solutions that ensure highly reliable device operations throughout their lifespan.
Since LBIST fault coverage can be unacceptably low for a feasible pattern count as compared to deterministic test sets, early BIST schemes employed weighted random patterns (WRP) to deal with the test data volume burden. These patterns bias the input signal probabilities to maximize the likelihood of generating the desired patterns. The WRP storage depends on the number of weight sets needed to achieve acceptable fault coverage. If the volume of stored data is to be reduced, many more test patterns than deterministic tests need to be applied. On the other hand, if test time is of concern, the storage size needs to be increased. One weighted random patterns-based BIST scheme is described by A. Jas et al., in “Weighted pseudorandom hybrid BIST,” vol. 12, pp. 1277-1283, December, 2004.
Alternatively, desired test stimuli may be obtained by perturbing pseudorandom vectors. One example is described by A.-W. Hakmi et al., in “Programmable deterministic built-in self-test,” Proc. ITC, 2007, paper 18.1.
There also exist hybrid BIST schemes in which deterministic patterns are stored on a tester in a compressed form, and then use the existing BIST infrastructure to perform a vector decompression. These deterministic top-up patterns target random-pattern-resistant faults, or faults that are difficult to be detected by random patterns. One hybrid BIST scheme is described by D. Das et al., in “Reducing test data volume using external/LBIST hybrid test patterns,” Proc. ITC, 2000, pp. 115-122.
Instead of using a combination of random test patterns and deterministic patterns or perturbing random test patterns, one can work with clusters of patterns comprising a deterministic parent central vector and its derivatives produced in a random or a deterministic fashion. An example of this approach is the Star-BIST scheme described by K.-H. Tsai et al., in “Star test: the theory and its applications,” vol. 19, pp. 1052-1064, September, 2000, which is incorporated herein by reference. In the Star-BIST scheme, each of parent ATPG patterns is subject to selective random flipping of its bits to generate a pattern cluster. The scheme requires complex on-chip test logic whose implementation makes use of scan order, polarity between the neighboring scan cells, control points inserted between them, and a waveform generator. With these features the scan may behave like a ROM capable of encoding several deterministic test vectors.
Challenges remain in developing deterministic BIST schemes that employ simple hardware and offer flexible tradeoffs between test coverage and volume of stored test data while maintaining test time within reasonable limits.